The invention relates to semiconductor devices and more particularly to a high capacitance and low-leakage integrated trench capacitor structure and a method for fabricating the same. The method is fully compatible with the advanced semiconductor manufacturing technologies, such as dielectric-filled trench isolation technique to fabricate high density single device memory cells.
Dynamic random access memories have been under active investigation by semiconductor manufacturers. According to the recent developments in this technology, fabrication of high density dynamic memory chips typically requires two device elements per storage cell, an active device (either a bipolar transistor or field effect transistor) and a passive device (e.g., capacitor). U.S. Pat. Nos. 3,387,286 to R. H. Dennard and 3,876,992 to W. D. Pricer, respectively, both of which are assigned to the present assignee, are representative of the prior art teachings of such dynamic memory structures.
In order to meet the ever-demanding requirements of higher integration density and superior performance of these memory structures, it is imperative that the capacitor element possess characteristics (both physical and electrical) which are consistent with these requirements. Among the different parameters which determine these capacitor characteristics, two are of significant importance: the surface area of the capacitor (which not only determines the capacitance but also the number of cells to be integrated in one chip) and leakage currents (which directly impact the ability of the capacitor to store the charge during the time between refresh cycles).
Accordingly, a dynamic memory must have very low PN junction leakage currents in its storage node, even at elevated temperatures, e.g. 100.degree. C. and at the same time should also have a large capacitance in the storage node.
These two requirements tend to be matually exclusive if the charges are stored in one of the PN junctions of the device. The reason is obvious, low leakage calls for lightly doped junctions but high capacitance calls for high doping levels.
For a long time, the storage capacitor for dynamic memory cells consisted of one of the three junctions (emitter-base junction, collector-base junction or collector-substrate junction) associated with a bipolar transistor or the drain-substrate junction associated with a field effect transistor (FET). In the bipolar transistor situation, more specifically in case of a typical NPN device, it is well known that the leakage of the base-emitter junction is 2-3 orders of magnitude higher than that of the collector-base junction. If the charges are stored in the base of a bipolar transistor, they tend to leak away very fast because of the combined leakage of the base-emitter and base-collector junctions. If the charges are stored in the emitter, they are still subject to the high leakage of the emitter-base junction. On the other hand, if the charges are stored in a floating collector it tends to have about three orders of magnitude less leakage than the two other junctions rendering the floating collector as the desirable charge storage medium.
However, it has been recently recognized that a low-leakage and high-capacitance storage node cannot be obtained by utilizing junction capacitances alone and that an additional storage capacitor is necessary. Accordingly, attempts were made to design an additional capacitor in integration with the transistor device and thereby obtaining the basic cell. A metal-oxide-silicon (MOS) type transistor and storage capacitor combination is disclosed in U.S. Pat. No. 4,255,945. In an effort to minimize the consumption of the chip real estate, which is at a premium, the buried polysilicon-oxide-silicon (POS) type storage capacitor has been proposed in the article by C. G. Jambotkar entitled "Very Dense One-Device FET Memory Cell", IBM Technical Disclosure Bulletin Vol. 25, No. 2, pp. 593-596, July 1982. This article discloses a one-device FET cell in which the drain of the FET is connected in series to the POS capacitor.
Both types of these prior art capacitor structures have demonstrated their capability for having relatively low leakage currents as compared to PN junction capacitances in the design of dynamic one-device memory cells. Also, because the POS-type capacitor does not extend over the surface area of the silicon substrate, but instead is integrated vertically, thereby obtaining significant gain in integration density, it has received wide acceptance in the industry.
In this connection, reference is made to U.S. Pat. No. 4,353,086 to R. J. Jaccodine et al. This reference describes a random access memory (RAM) in which individual cells, including an access transistor and a storage capacitor, are formed in mesas formed on a silicon chip. For each cell, the transistor is formed on the top surface of the mesa and the capacitor is formed in the mesa sidewalls. One plate of the storage capacitor is obtained by a doped region formed into the sidewall of the mesa, and the other plate is obtained by doped polycrystalline silicon which fills the groove surrounding the mesa. An insulating layer on the wall of the mesa serves as the capacitor dielectric.
The structure disclosed in Jaccodine et al. although seen as being a significant achievement in the progress of FET dynamic RAMs, it is believed to have a number of disadvantages. Since the isolation grooves are filled with doped polysilicon, the latter acts as a common plate for all capacitors shared by a particular groove. In other words, all the capacitors that share a groove have a common node (which is connected to the ground in that reference). This means that all the capacitors formed on the chip have one plate connected to that common node due to the electrical continuity provided by the polysilicon filling all the grooves of the chip.
From a process standpoint, the Jaccodine et al. process requires a specifically tailored and controlled ion implantation or diffusion step to form the doped regions constituting the one plate of the capacitor. Such a process is unsuitable in a high volume production environment. Also, to prevent formation of parasitic channels in the mesa surface region between the source/drain and the capacitor plate, the patented device requires a channel stop positioned adjacent to the capacitor plate in the mesa surface region. The channel stop-forming step further detracts the process from a high volume and high yield production environment. Yet another drawback of the Jaccodine et al. structure is that, due to the presence of the conductive capacitor plate on the mesa sidewall, the source/drain of the FET cannot be butted against the isolation grooves. Consequently, high integration density cannot be achieved. Finally, the Jaccodine et al. structure must have polysilicon-filled trench isolation, it suffers from the disadvantage associated with polysilicon trench isolation such as generation of defects in the silicon due to thermal mismatch between the trench-fill material and the trench insulator liner and that between the trench liner and the silicon substrate.
Accordingly, it is an object of the invention to provide a high-capacitance and low-leakage integrated capacitor structure and a method for making the same which meets the requirements of manufacturability with acceptable yields.
It is anothe object of the present invention to provide a high-capacitance, low-leakage self-aligned mesa shaped integrated capacitor structure and a method for making the same which is fully compatible with bipolar and/or FET technology with self alignment and abutment capabilities.
It is another object of the present invention to provide a low-leakage, high-capacitance, self-aligned mesa-shaped integrated capacitor structure and a method for making the same which is fully compatible with polyimide-filled deep trench isolation scheme.
It is another object of the present invention to provide a low-leakage, high-capacitance, self-aligned mesa-shaped integrated capacitor and a method for making the same which renders one capacitor electrically independent from other capacitors formed in adjacent mesas, thereby providing the unique design option of connecting capacitors where needed.
It is still another object of the present invention to provide a high density, high performance dynamic memory by incorporating the aforementioned capacitor into a single device memory cell, the active device thereof being either a bipolar or FET or a combination bipolar-FET structure.
It is still another object of the invention to provide a high density, high performance dynamic memory by incorporating the aforementioned capacitor into a single device memory cell with minimal increase in cell area.
It is still another object of the present invention to provide a low-leakage high-capacitance, self-aligned mesa-shaped integrated capacitor structure and a method for making the same which has the capability of selectively providing the capacitor only in the memory cells while not providing a capacitor in the peripheral circuits.
These and other related objects are attained with the high capacitance, low leakage, self aligned mesa shaped integrated capacitor structure of the present invention. The capacitor of the present invention overcomes all the disadvantages of the prior art structures and, in particular, the various problems associated with integrating an active device and a capacitor in a very dense configuration to form high performance dynamic one device cell.
The capacitor structure is of the polysiliconoxide-silicon (POS) type and is formed on the sidewalls of a mesa-shaped silicon regions delineated and surrounded by an isolation trench formed in the silicon material. The mesa-shaped silicon material serves as the first plate of the capacitor. A thin dielectric layer formed on the vertical sidewalls of the mesa serves as the capacitor insulator and a thin conductive polysilicon layer formed directly over the capacitor insulator serves as the second plate of the capacitor. In other words, in a preferred embodiment the thin polysilicon layer is wrapped around the outer peripheral surface of the mesa. Since the second plate of the capacitor is formed as a coating of the vertical sidewalls of the mesa it encompasses a large area. Consequently, it gives rise to a large storage capacitance without increasing the cell size. The essential feature of the invention is that the thin polysilicon layer which acts as the second plate of the capacitor does not fill the trench, but merely wraps around the trench sidewalls. The trench itself is filled with a plastic, low temperature deposition material, such as polyimide for device isolation purposes. In accordance with a more specific aspect of the invention, the silicon substrate is of a first type of conductivity (e.g., P-) which is covered with an epitaxial silicon layer of the opposite type (e.g., N-). The stud- or mesa-shaped locations of the substrate containing the capacitor are provided with a heavily doped buried layer (e.g., N+) which can also be used as a low resistance subcollector of a bipolar transistor located in the silicon stud/mesa. The trench is etched into the substrate penetrating to a desired depth. With this structure, the capacitor is electrically isolated from any PN junction located in adjacent mesas, and in addition, any plate of any capacitor may be connected where needed without the design limitation of having a common connection node.
Integrating the POS capacitor into the sidewalls results in a large storage capacitor because the surface area of the plate is the product of the depth of the trench and the perimeter of the mesa. It is therefore, easy to adjust the capacitance value either by adjusting the top planar dimensions of the mesa, the depth of the trench or both of these parameters. In addition, this particular structure significantly reduces PN junction leakage currents. When the mesa includes an active device, the presence of this capacitor results in little or no increase in the device area thereby obtaining a very dense integrated circuit structure.